Fast-locking all-digital phase-locked loop with digitally controlled oscillator tuning word estimating and presetting

Abstract

Design of a fast-locking phase-locked loop (PLL) is one of the major challenges in today's wireless communications. A recently reported digitally controlled oscillator (DCO)-based all-digital PLL (ADPLL) can achieve an ultrashort settling time of 10 µs. This study describes a new DCO tuning word (OTW) presetting technique for the ADPLL to further reduce its settling time. Estimating the required OTW is the most crucial issue for presetting. Two methods are proposed here to estimate the required OTW. One method is using a foreground calibration block to eliminate the effect of DCO gain (KDCO) estimation error (ɛK) and then directly calculating the required OTW for the process/voltage/temperature calibration (PVT-calibration) mode of the ADPLL. The other method is using a new counter-based mode switching controller (CB-MSC) to estimate the required OTW for the acquisition mode and tracking mode. This method is based on the ADPLL's inherent characteristic of frequency toggling and is independent of loop parameters. Furthermore, our proposed presetting technique can be used with the dynamic loop bandwidth control technique together. The ADPLL with the proposed OTW estimating and presetting block is designed using very-high-speed integrated circuit hardware description language and simulated in ModelSim environment. Simulation results demonstrate that a minimum settling time of 2.9 µs is achieved and the improvement is about 40–50% on average compared with the ADPLL without our techniques.