A CMOS Envelope-Tracking Transmitter With an On-Chip Common-Gate Voltage Modulation Linearizer

Abstract

This letter presents a fully integrated CMOS envelope-tracking transmitter with an on-chip common-gate voltage modulation linearizer that achieves an average output power of 26/23.5 dBm with a PAE of 33/28%, an ACLR of -33 / -32.5 dBc at a frequency of 1.9 GHz for 3.84 MHz BW 3.5 dB PAPR WCDMA and 5 MHz BW 7.5 dB PAPR LTE signals in an 0.18-μm CMOS process. The CMOS ET transmitter is integrated with an envelope amplifier, two pairs of saturated power amplifiers, and an on-chip linearizer. The total chip size is 2.5 × 1.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with the input/output on-chip transformers and matching networks.