Novel approaches to quantify failure probability due to process variations in nano-scale CMOS logic

Abstract

Estimating the failure probability of nano-scale generic logic cells is a key point for the evaluation of digital system reliability. Noise-induced input variations with process-induced threshold voltage variations affect the probability of correct operation of logic cells. This work quantitatively analyses the probability of invalid output of a cell by introducing novel analytical and semi-analytical approaches in comparison with SPICE Monte-Carlo verification approach.