Functional Partitioning and Simulation of Digital Circuits

Abstract

In this paper we present a method for obtaining a functional partitioning of the logic of a computer. It is shown that given a basic function to be performed, such as addition, the computer logic can be partitioned into four disjoint sets, namely the active information logic I, the semiactive flip-flops l, the activated control logic c, and the dormant logic D. Techniques involved in implementing the partitioning algorithm such as an event-directed simulator and three-value simulation are discussed. An application of this partitioning scheme as part of a large logic simulation system is described.