Multi-level 40nm WO<inf>X</inf> resistive memory with excellent reliability

Abstract

40nm WO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub> ReRAM has several unique characteristics that are very favorable for MLC application. (1) Although the resistance has strong temperature dependence (as for all ReRAM's) the J-V characteristics can be accurately described, thus all MLC levels are easily modeled. (2) The device is immune to over-erase, thus allow fast MLC programming. (3) The programming is self-converging (as Flash memories) and is independent of history. Thus an algorithm similar to ISPP (Incremental Step Pulse Programming), commonly used by MLC NAND flash, is designed to achieve accurate MLC states. Consequently, fast 50ns switching, 2-bit/cell and 3-bit/cell MLC states with good cycling characteristics and low read disturbance (>; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> ) is achieved.