A comparative study of thermal stress induced dislocation generation in pulled GaAs, InP, and Si crystals

Abstract

We have extended the recently developed quasisteady-state heat transfer/thermal stress model for glide dislocation generation in Czochralski pulled GaAs to InP and Si. The calculated results are displayed by means of (a) dislocation density contour lines for {100} wafers and (b) a novel ambient temperature (Ta) stability diagram. The latter representation explicitly shows the progressive elimination of dislocation-free regions with decreasing Ta in GaAs, InP, and Si. It is predicted that unless the diameter is unusually small (∼1 cm), glide dislocations appear at the periphery of both GaAs and InP grown by LEC at a Ta which is only ∼10 °K below their respective melting points. With decreasing Ta the dislocations rapidly spread throughout the interior. In contrast, an 8-cm-diam Si crystal is dislocation-free even at a Ta about 40 °K below the melting point. At this critical Ta glide dislocations which are confined to the circumference begin to generate. Thus, in accord with current crystal growth experience, Si exhibits a decisive advantage over the compounds in its resistance to thermal stress-induced slipping. This is likely to be due to the elemental solid’s large critical resolved shear stress and thermal conductivity.