IEE Proceedings - Computers and Digital Techniques · 1997 · 15 citations · 7 references
EngineeringComputer EngineeringComputer ScienceFault ToleranceFault-tolerant ComputingVlsi DesignError DetectionFault Tolerance DesignHardware Fault ToleranceRedundancy TechniquesConcurrent Error DetectionFault Tolerance MechanismsFault Tolerant ArchitecturesFault-tolerant ArchitectureFault-tolerant DesignFault-tolerant Processor DesignSystolic Array DesignSystolic Arrays
A systematic approach for designing a fault-tolerant systolic array using space and/or time redundancy is proposed. The approach is based on a fault-tolerant mapping theory which relates space–time mapping and concurrent error detection techniques. By this design approach, the resulting systolic array is fault tolerant and achieves the optimal space–time product. In addition, it has the capability to compute more problem instances simultaneously without extra cost.
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On the design of algorithms for VLSI systolic arrays
Dan Moldovan · Proceedings of the IEEE · 1983 · 392 citations