2010 · 38 citations · 6 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureLow-power DesignMicroelectronicsClock ManagementMicroarchitecture DesignMulticore Processor DesignPower ManagementProcessor Core DesignProcessor MicroarchitectureClock Buffer DesignHigh-speed Cmos DesignLow-power MicroarchitecturePower-performance-area TradeoffsReconfigurable Embedded ProcessorsReconfigurable Processor ArchitecturesReconfigurable System-on-chip ArchitecturesSystem-on-chip Power Management
A 648 MHz 153.8 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> 45 nm CMOS SoC integrates eight general-purpose CPUs, four dynamically reconfigurable processors, two 1024-way matrix-processors, peripherals and interfaces. Using core enhancement, DDR3-I/F improvement and clock buffer deactivation, this SoC achieves 37.3 GOPS/W at 1.15 V.
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A 342mW mobile application processor with full-HD multi-standard video codec
Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda et al. · 2009 · 15 citations