Radiation Hardening of P-MOS Devices by Optimization of the Thermal Si02 Gate Insulator

Abstract

It has been found for p-channel MOS devices that considerably better radiation tolerance than generally believed possible can be obtained with gate insulators of thermally grown SiO2, provided that the processing conditions are optimized for radiation resistance. The oxidation ambient and temperature, the post-oxidation annealing temperature, the silicon orientation, and the method of depositing the gate metal all have pronounced effects on the radiation-induced degradation. With these parameters optimized for radiation hardness, gate threshold shifts of less than one volt after 1 × 106 rads (Si) can be obtained over the entire range of gate biases from 0 to -30 volts. This paper describes these findings and their applicability to the fabrication of radiation-hardened MOS circuits.