IEEE Transactions on Computers · 1986 · 52 citations · 12 references
EngineeringComputer EngineeringFault ToleranceFault-tolerant ComputingField-programmable Gate ArraysArray ProcessingDesign For TestabilityUnit CellsCombinational Cell DesignFiltersMatrix MultiplicationSystolic Array DesignSystolic ArraysTestabilityTestability Engineering
Two sets of conditions are derived that make one- dimensional bilateral arrays of combinational cells testable for single faulty cells. The test sequences are preset and, in the worst case, grow quadratically with the size of the array. Conditions for testability in linear time are also derived. The basic cell can operate at the bit or at the word level. An implementation of FIR filters using (systolic) one-dimensional bilateral arrays of cells, which can be considered combinational at the word level, is presented as an example. A straightforward generalization for the two- dimensional case is made; a systolic array used for matrix multiplication is presented as an example for this case.
12
Easily Testable Iterative Systems
Arthur Friedman · IEEE Transactions on Computers · 1973 · 253 citations
Testing for faults in combinational cellular logic arrays
William H. Kautz · 1967 · 175 citations
Design of Easily Testable Bit-Sliced Systems
Sridhar, Hayes · IEEE Transactions on Computers · 1981 · 95 citations
A Testable Design of Iterative Logic Arrays
Parthasarathy, Reddy · IEEE Transactions on Computers · 1981 · 92 citations