IEEE Journal of Solid-State Circuits · 1988 · 13 citations · 8 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureLow-power DesignMicroelectronicsCmos Circuit DesignDigital Signal ProcessingLow-power Digital Circuit DesignParallel ArchitecturesArithmetic CircuitsArithmetic Logic Unit DesignLow-power AddersLow-power Arithmetic CircuitsLow-power MultipliersMulti-digit MultiplicationMultiplier DesignMultipliers
The design of a 4*4-bit multiplier using the modified Booth's algorithm in 2- mu m NMOS technology is discussed. The main features of this chip are its 62.5-MHz operating frequency and 31.5-mW power dissipation. The chip occupies an area of 1.37 mm/sup 2/. A novel adder-cum-subtractor circuit was designed to realize the arithmetic processing part.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
8
High-Speed Arithmetic in Binary Computers
O. L. Macsorley · Proceedings of the IRE · 1961 · 622 citations
A Pipelined 330-MHz Multiplier
Thomas Noll, D. Schmitt‐Landsiedel, H. Klär et al. · IEEE Journal of Solid-State Circuits · 1986 · 69 citations
Engineering, Computer Engineering, Electrical Engineering +17