84 Gbit/s SiGe BiCMOS duobinary serial data link including Serialiser/Deserialiser (SERDES) and 5‐tap FFE

Abstract

The increasing demand for bandwidth fuels the development towards high data rate electrical serial links. These links generally suffer from considerable frequency‐dependent loss, introducing the need for equalisation at 10 Gbit/s and higher. Modulation schemes with improved spectral efficiency, with respect to non‐retrun to zero (NRZ), combined with feed‐forward equalisation (FFE), allow increasing the chip‐to‐chip data rate with the drawback of a more complex, e.g. multi‐level, receiver (Rx). The use of duobinary modulation (DB) is presented to realise a high‐speed serial link. The increase in complexity of a DB Rx is limited, whereas the required channel bandwidth compared with NRZ is reduced. Furthermore, the need for equalisation when compared with PAM4 is reduced as the required roll‐off that is needed to create a duobinary modulated signal from an NRZ stream can incorporate the frequency‐dependent loss of the link.