Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion

Abstract

The minimum clock period in semisynchronous framework might be reduced if delays are increased by delay insertion. We propose a delay insertion algorithm to reduce the minimum clock period in semisynchronous framework. We show that the proposed algorithm achieves the minimum clock period in semisynchronous framework by delay insertion if the delay of each element is unique. Experiments show that the amount of inserting delay and computational time are smaller than the conventional algorithm.