Design and package technology development of Face-to-Face die stacking as a low cost alternative for 3D IC integration

Abstract

F2F stacking provides an alternative 3D packaging solution for multi-chip integration without use of TSV. High density interconnection can be achieved with direct Face-to-Face (F2F) stacking to enable high bandwidth die to die interface. Simplified stacking process and lower development cost make F2F stacking an attractive solution for cost sensitive applications. A comparative study of performance was performed on F2F stacked Field Programmable Gate Array (FPGA) die in a flip chip organic package. The paper first presents thermal analysis to address power density increase, hot spot and temperature variations in the F2F package. Next the paper focuses on electrical performance validation including both IO and power delivery analysis. With appropriate chip design and optimization, we demonstrate that F2F stacking induced thermal and electrical impacts can be controlled to meet speed and performance specs equivalent to 2D system. The manufacturing design rules have been optimized to meet yield requirements as well as ensuring product reliability.