Engineering single NMOS and PMOS output buffers for maximum failure voltage in advanced CMOS technologies

Abstract

In this paper we propose new circuit design options for increasing the ldquoeffectiverdquo failure voltage (Vt2) of both NMOS and PMOS output buffer transistors, thereby helping to protect these fragile devices. Using experimental data, device and circuit simulations we demonstrate how placing a series resistor and either a bias circuit for the buffer gates or secondary ESD diodes may significantly increase Vt2.