Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation

Upset hardened memory design for submicron CMOS technology

T. Calin, M. Nicolaidis, Raoul Velazco · IEEE Transactions on Nuclear Science · 1996 · 1.1K citations

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Latch Susceptibility to Transient Faults and New Hardening Approach

M. Omaña, Daniele Rossi, Cecilia Metra · IEEE Transactions on Computers · 2007 · 140 citations

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Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies[Note 1]

Mahdi Fazeli, Seyed G. Miremadi, Alireza Ejlali et al. · IET Computers & Digital Techniques · 2009 · 130 citations

Engineering, Computer Engineering, Electrical Engineering +17

Analysis and Design of Nanoscale CMOS Storage Elements for Single-Event Hardening With Multiple-Node Upset

Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi · IEEE Transactions on Device and Materials Reliability · 2011 · 112 citations

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High Performance, Low Cost, and Robust Soft Error Tolerant Latch Designs for Nanoscale CMOS Technology

Haiqing Nan, Ken Choi · IEEE Transactions on Circuits and Systems I Regular Papers · 2012 · 109 citations

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