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Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation

Low-power ElectronicsHardware SecurityElectrical EngineeringLatch DesignsEngineeringVlsi DesignProcess VariationCircuit SystemNanoelectronicsBias Temperature InstabilityComputer ArchitectureCmos TechnologyComputer EngineeringMicroelectronicsNano-scale Cmos Technology