Publication | Closed Access
Electrical Waveform Mediated Through-Mask Deposition of Solder Bumps for Wafer Level Packaging
13
Citations
10
References
2004
Year
EngineeringMechanical EngineeringElectrical WaveformWafer Scale ProcessingAdvanced Packaging (Semiconductors)Electronic PackagingWafer Level PackagingMaterials ScienceMaterials EngineeringElectrical EngineeringPowder MetallurgyChip On BoardFabrication TechniqueChip AttachmentElectrical InsulationMetal FormingMicroelectronics3D PrintingMicrostructureMicrofabricationApplied PhysicsDirected Energy DepositionSolder BumpsWaveform MediationAlloy CastingMetal Processing
Electrical waveform mediated through-mask deposition of solder bumps was investigated with several types of plating baths for wafer level packaging applications. The influence of varying duty cycle in the presence of additives on deposit properties including shape evolution within the cavity, abnormal growth, surface morphology, alloy composition, and thickness distribution was evaluated at a fixed, moderate frequency. Waveform mediation with properly selected duty cycles (i) improved surface flatness and morphology of deposits when the shape ratio with dc deposition was less than 1, (ii) suppressed the probability of abnormal growth (nonhomogeneous growth such as large nodules), (iii) reduced grain sizes resulting in smoother surfaces, and modulated alloy composition at a given bath and process condition. With decreasing duty cycle, the thickness distribution within the feature, pattern, and workpiece also changed due to the increased influence of primary current distribution. The fraction of current flowing along the cavity edge, die edge (when the space between dice is much larger than the bump pitch), and wafer edge seems to increase with decreasing duty cycle. © 2004 The Electrochemical Society. All rights reserved.
| Year | Citations | |
|---|---|---|
Page 1
Page 1