PACT HDL

TLDR

Chip fabrication technology is moving into sub‑micron levels, demanding more logic and faster design, so high‑level languages like C/C++ are gaining popularity for hardware description and synthesis, while increasing logic density raises power dissipation concerns. PACT HDL is a C‑to‑HDL compiler that merges automated hardware synthesis of high‑level algorithms with power and performance optimizations, targets arbitrary hardware architectures—especially SoC environments with reprogrammable and application‑specific hardware—and is intended for applications such as image and signal processing. The compiler is modular and flexible, allowing optimizations to be applied in any order and at different stages, and it generates industry‑standard HDL codes (RTL Verilog and VHDL) that can be synthesized and profiled for power with commercial tools. This is the first paper on the PACT compiler project, presenting the compiler framework and introductory optimizations.

Abstract

Chip fabrication technology continues to plunge deeper into sub-micron levels requiring hardware designers to utilize ever-increasing amounts of logic and shorten design time. Toward that end, high-level languages such as C/C++ are becoming popular for hardware description and synthesis in order to more quickly leverage complex algorithms. Similarly, as logic density increases due to technology, power dissipation becomes a progressively more important metric of hardware design. PACT HDL, a C to HDL compiler, merges automated hardware synthesis of high-level algorithms with power and performance optimizations and targets arbitrary hardware architectures, particularly in a System on a Chip (SoC) setting that incorporates reprogrammable and application-specific hardware. PACT HDL is intended for applications well suited to custom hardware implementation such as image and signal processing codes. By making the compiler modular and flexible, optimizations may be executed in any order and at different levels in the compilation process. PACT HDL generates industry standard HDL codes, such as RTL Verilog and VHDL, which may be synthesized and profiled for power using commercial tools. This is the first paper on the PACT compiler project in a series. The compiler framework and introductory optimizations are presented. Later papers will focus on these and other optimizations in detail.