A Sub-1W to 2W Low-Power IA Processor for Mobile Internet Devices and Ultra-Mobile PCs in 45nm Hi-¿ Metal Gate CMOS

Abstract

This paper describes a low-power Intel* Architecture (IA) processor specifically designed for Mobile Internet Devices (MID) and Ultra- Mobile PCs (UMPC) where average power consumed is in the order of a few hundred mW (as measured by MobileMark'05 OP @ 60 nits brightness) with performance similar to mainstream Ultra-Mobile PCs. The design consists of an in-order pipeline capable of issuing 2 instructions per cycle supporting 2 threads, 32KB instruction and 24KB data LI caches, independent integer and floating point execution units, x86 front end execution unit, a 512KB L2 cache and a 533 MT/s dual-mode (GTL and CMOS) front-side-bus (FSB). The design contains 47 M transistors in a die size under 25 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> manufactured in a 9-metal 45nm CMOS process with optimized transistors for low leakage packaged in a Halide-Free 441 ball, 14x13 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> muFCBGA. Thermal Design Power (TDP) consumption is measured at 2 W using a synthetic power-virus test at a frequency of 2 GHz.