Exploiting Slack Time in Dynamically Reconfigurable Processor Architectures

Abstract

In dynamically reconfigurable processors, different contexts as well as different data paths within one context usually vary in their execution time. Voltage scaling offers the ability to utilize this variation to reduce power consumption. In this paper, we propose a dual-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> dynamically reconfigurable processor architecture which utilizes the varying execution time to reduce dynamic power consumption without adapting the clock frequency. Gate-level simulations reveal that the proposed dual-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> architecture reduces the power consumption of a processing element up to 22.1% and the total power consumption up to 10.5% compared to a single voltage architecture instance.