Paul S. Zuchowski

Managing power and performance for System-on-Chip designs using Voltage Islands

David E. Lackey, Paul S. Zuchowski, Thomas Bednar et al. · Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design · 2002 · 292 citations

Hardware Security, Power-aware Computing, Electrical Engineering +14

A hybrid ASIC and FPGA architecture

Paul S. Zuchowski, Christopher B. Reynolds, Richard J. Grupp et al. · Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design · 2002 · 119 citations

Engineering, Fpga Architecture, Computer Architecture +18

Process and environmental variation impacts on ASIC timing

Paul S. Zuchowski, Peter Habitz, Jerry Hayes et al. · 2005 · 105 citations

Engineering, Vlsi Design, Semiconductor Process Node +16

A hybrid ASIC and FPGA architecture

Paul S. Zuchowski, Christopher B. Reynolds, Richard J. Grupp et al. · IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002. · 2003 · 45 citations

Hardware Security, System On Chip, Hybrid Asic/fpga Architecture +12

Issues and strategies for the physical design of system-on-a-chip ASICs

Thomas Bednar, P. Buffet, R. J. Darden et al. · IBM Journal of Research and Development · 2002 · 17 citations

Engineering, Electronic Design, Computer Architecture +18