2008 · 12 citations · 11 references
ComputingComputer EngineeringComputer ScienceComputer ArchitectureComputer NetworksFormal MethodsDeductive VerificationDesign SpecificationExecutable System ModelsNetwork ArchitectureNetwork-on-chip DesignSoftware-defined NetworkingExecutable ModelsExecutable SpecificationsFormal Hardware VerificationFormal ModelingHardware Model CheckingInterconnect VerificationModel-based Hardware DesignNetwork Verification
We describe an enhanced generic model for Networks-on-Chip (NoCs), implemented in the executable logic of the ACL2 theorem prover. The model is meant for serving as a formal reference for the specification, validation, and simulation at the initial design phase. Instantiated on a specific NoC, the model may be used for formal proofs and for simulation. The methodology is illustrated on HERMES.
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HERMES: an infrastructure for low area overhead packet-switching networks on chip
Fernando Moraes, Ney Calazans, Aline Mello et al. · Integration · 2004 · 510 citations
An interconnect architecture for networking systems on chips
Faraydon Karim, Anh Nguyen, S. Dey · IEEE Micro · 2002 · 265 citations