Hardware Model Checking

Hardware Model Checking is a formal verification technique that systematically explores the state space of a hardware design to verify whether its behavior conforms to a given temporal logic specification, distinguishing it from other verification methods by its exhaustive, automated, and mathematical approach to detecting design errors.

371

Publications

16.2K

Citations

849

Authors

287

Institutions

Publications per year

2017–2026

40

Authors

849

  1. RD
    Rolf Drechsler

    University of Bremen, Germany

    8 publications · 219 citations

    8

    h-index

  2. RE
    Randal E. Bryant

    Carnegie Mellon University, United States

    8 publications · 561 citations

    8

    h-index

  3. EM
    E. M. Clarke

    Carnegie Mellon University, United States

    7 publications · 938 citations

    7

    h-index

  4. DK
    Daniel Kroening

    University of Oxford, United Kingdom

    7 publications · 245 citations

    7

    h-index

  5. MN
    Miroslav N. Velev

    Carnegie Mellon University, United States

    7 publications · 362 citations

    7

    h-index

1–5 of 849

Venues

  1. 9

    h-index

  2. Electronic Notes in Theoretical Computer Science

    ENTCS · 8 publications · 360 citations

    8

    h-index

  3. IEEE Design & Test of Computers

    7 publications · 428 citations

    7

    h-index

  4. Design Automation Conference

    Conference · 5 publications · 86 citations

    5

    h-index

  5. Formal Methods in System Design

    4 publications · 90 citations

    4

    h-index

1–5