Hardware Model Checking
Hardware Model Checking is a formal verification technique that systematically explores the state space of a hardware design to verify whether its behavior conforms to a given temporal logic specification, distinguishing it from other verification methods by its exhaustive, automated, and mathematical approach to detecting design errors.
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16.2K
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Authors
287
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2017–2026
40
371
Counterexample-guided abstraction refinement for symbolic model checking
Edmund M. Clarke, Orna Grümberg, Somesh Jha et al. · Journal of the ACM · 2003 · 991 citations
Symbolic model checking using SAT procedures instead of BDDs
Armin Biere, Alessandro Cimatti, E. M. Clarke et al. · 1999 · 697 citations
Roberto Bagnara, Patricia M. Hill, Enea Zaffanella · Science of Computer Programming · 2008 · 466 citations
Model checking and abstraction
Edmund M. Clarke, Orna Grümberg, David E. Long · 1992 · 353 citations · Full text
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Carnegie Mellon University
Pittsburgh, United States
20 h-index
56 publications
7.3K citations
Stanford University
Stanford, United States
15 h-index
59 publications
1.8K citations
Intel (United States)
Santa Clara, United States
15 h-index
38 publications
1.4K citations
IBM (United States)
Armonk, United States
12 h-index
32 publications
2.6K citations

University of British Columbia
Vancouver, Canada
11 h-index
24 publications
1.4K citations
The University of Texas at Austin
Austin, United States
11 h-index
20 publications
697 citations
University of California, Berkeley
Berkeley, United States
10 h-index
27 publications
782 citations
Princeton University
Princeton, United States
9 h-index
25 publications
1.3K citations
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9 publications · 350 citations
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ENTCS · 8 publications · 360 citations
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7 publications · 428 citations
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Conference · 5 publications · 86 citations
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4 publications · 90 citations
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