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Implementation of Short-Term Plasticity and Long-Term Potentiation in a Synapse Using Si-Based Type of Charge-Trap Memory
31
Citations
15
References
2015
Year
Non-volatile MemoryEngineeringEmerging Memory TechnologyShort-term PlasticityCharge-trap MemoryNeurochipSocial SciencesBiological SynapseMemory DeviceMemory DevicesNeuromorphic EngineeringElectrical EngineeringElectronic MemoryTrapped ChargeComputer EngineeringMicroelectronicsSynaptic PlasticityComputational NeuroscienceBioelectronicsLong-term PotentiationNeuroscienceSemiconductor Memory
We present a novel silicon-based type of charge-trap memory using Al/HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> /Si structure mimicking memory functions in a biological synapse. The quantity of the trapped charge in the proposed Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> stack is estimated by measuring the capacitance over time, which can be regarded as synaptic weight changes. By applying repeated voltage pulses at periodic intervals of different times, reliable short-term plasticity and long-term potentiation properties are obtained along with their transition behavior. This architecture is compatible with the CMOS process and shows great promise as an essential part for the implementation of an electrical neuromorphic system.
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