The role of radiation effects in SOI technology development

Abstract

The technical development of radiation resistant CMOS/SOI technologies is reviewed. Inherent hardness of SOI to dose rate upset and latchup has leveraged major developments of SOI technologies. TID hardness for up to the 150nm node was addressed by process hardening. Inherent hardness of 45nm and 32nm technologies reduced the need for TID hardening. As technology is scaled to 28nm and 14nm nodes TID hardening is again required. SEU hardening is addressed by circuit design for a wide range of technologies with significant SEU improvement for 28nm and 14nm is observed.