2010 · 12 citations · 12 references
EngineeringComputer EngineeringComputer ScienceAlgorithmsComputer ArchitectureField-programmable Gate ArraysConfigurable Logic BlocksDigital Signal ProcessingField-programmable Gate Array ArchitectureFpga ArchitectureHardware AccelerationTiming AnalysisDesign CriteriaDigital Signal Processing BlocksDiscrete Fourier TransformFast Fourier TransformFast Fourier Transform MultiplicationFeedback DelayField-programmable Gate Arrays (Fpgas)Fourier Transform
In this paper, we propose higher point FFT (fast Fourier transform) algorithms for a single delay feedback pipelined FFT architecture considering the 4096-point FFT. These algorithms are different from each other in terms of twiddle factor multiplication. Twiddle factor multiplication complexity comparison is presented when implemented on Field-Programmable Gate Arrays (FPGAs) for all proposed algorithms. We also discuss the design criteria of the twiddle factor multiplication. Finally it is shown that there is a trade-off between twiddle factor memory complexity and switching activity in the introduced algorithms.
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