1/ <i>f</i> noise in gate-controlled planar silicon diodes

Abstract

Low-frequency excess noise in planar bipolar silicon devices was investigated by means of gate-controlled n+−p diodes. Within the range of parameter values covered in this investigation, it was found that the noise-power maxima invariably occur at gate bias voltages leading to depletion of majority carriers at the surface of the high-resistivity side of the p–n junction.