2012 · 11 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignDigital Integrated CircuitsLow-noise Circuit DesignLow-power Digital Circuit DesignMixed-signal Integrated Circuit DesignAnalog-digital ConversionAnalog-to-digital ConversionCmos Analog Circuit DesignCmos Analog Integrated CircuitsComparator DesignLinearityLow-noise DesignPower Consumption
This paper presents a 12-bit 1-MS/s SAR ADC incorporating a sampling capacitor-swapping technique. The proposed swapping technique effectively removes the capacitor- DAC middle-code transition error, resulting in improved linearity, without needing large capacitor size for good capacitor matching. Moreover, an on-the-fly programmable dynamic comparator is adopted in the design for meeting fast comparison as well as low-noise requirements with small power consumption. The ADC was fabricated in 0.11 μm CMOS. It consumes 16.47 μW at 0.9 V supply. Measured DNL and INL are 0.3 LSB and 0.56 LSB respectively. Measured SNR and SFDR are 67.5 dB and 87 dB respectively. ENOB is measured at 10.92 b, equivalent to a FOM of 8.47 fJ/conversion-step.
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A low-noise self-calibrating dynamic comparator for high-speed ADCs
Masaya Miyahara, Yusuke Asada, Daehwa Paik et al. · 2008 · 414 citations
Engineering, Computer Engineering, Electrical Engineering +17
A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation
Chun-Cheng Liu, Soon-Jyh Chang, Guan‐Ying Huang et al. · 2010 · 310 citations
A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS
Ying-Zu Lin, Soon-Jyh Chang, Ya-Ting Shyu et al. · 2011 · 16 citations
Engineering, Computer Engineering, Electrical Engineering +17