2011 · 16 citations · 8 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignDigital Integrated CircuitsDynamic Power ReductionLow-power Digital Circuit DesignMixed-signal Integrated Circuit DesignAnalog-digital ConversionAnalog-to-digital ConversionAnalog-to-digital ConvertersCmos Analog Circuit DesignCmos Analog Integrated CircuitsLinearityPower ConsumptionSettling Time
This paper presents a new subrange analog-to-digital converter (ADC): a binary-search coarse ADC + a SAR fine ADC. The binary-search ADC improves conversion speed and gives coarse capacitors longer settling time. This ADC uses an RC hybrid DAC to reduce the unit capacitor count by 2. The rotation function of coarse capacitors enhances capacitor array linearity. The prototype in 90-nm CMOS only occupies an active area of 0.06 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . From a 0.9-V supply, the power consumption is 0.32 and 0.58 mW at 10 and 25 MS/s, respectively. At 10 MS/s, the peak ENOB is 10.2 bit. At 25 MS/s, the peak ENOB is 9.9 bit and FOM is 29 fJ/conversion-step.
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A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation
Chun-Cheng Liu, Soon-Jyh Chang, Guan‐Ying Huang et al. · 2010 · 310 citations
An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS
Vito Giannini, Pierluigi Nuzzo, Vincenzo Chironi et al. · 2008 · 191 citations
Engineering, Computer Engineering, Electrical Engineering +17
A 10b 50MS/s 820&#x00B5;W SAR ADC with on-chip digital calibration
Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama et al. · 2010 · 102 citations
A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS
Ying-Zu Lin, Chun-Cheng Liu, Guan‐Ying Huang et al. · 2010 · 52 citations
Engineering, Computer Engineering, Electrical Engineering +17