Modeling of power delivery into 3D chips on silicon interposer

Abstract

While three-dimensional (3D) technology has several advantages for power delivery, an integrated chip-level, interposer-level, and package-level power distribution network in through-silicon-via (TSV)-based 3D system has to be modeled and evaluated. This paper reports on modeling of power delivery into 3D chip stacks on a silicon interposer/packaging substrate using a novel hybrid approach, i.e., combining the electromagnetic (EM) and analytic simulations. We intentionally partition the real stack-up structure of a 3D power network into separate components, i.e., package vias and traces, C-4 solders, interposer TSVs and planar wires, μ-C4 solders, chip TSVs, and on-chip power grids with node capacitors, decoupling capacitors and active current loads. All the passive RLGCs for each component are extracted using an EM simulation tool at a given working frequency point. We then assemble all the components back into a corresponding equivalent circuit model with those EM extracted RLGC values, thus to analyze the supply voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> )variation over time for 3D systems in a manner of maximum accuracy and efficiency.