Rigorous extraction of process variations for 65nm CMOS design

Abstract

Statistical circuit analysis and optimization are critical for robust nanoscale design. To accurately perform such analysis, primary process variation sources need to be identified and modeled for further circuit simulation. In this work, we present a rigorous method to extract process variations from <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in-situ</i> IV measurements. Transistor statistics are collected from a test chip fabricated in a 65 nm SOI process. We recognize gate length (L), threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) and mobility (mu) as the leading variation sources, due to the tremendous process challenge in lithography, channel doping, and stress. To decompose them, only three IV points are needed from the leakage and linear regions. Both L and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> variations are normally distributed, with negligible spatial correlation. By including extracted variations in the nominal model file, we can accurately predict the change of drive current in all process corners. The new extraction method guarantees excellent model matching with hardware for further statistical circuit analysis.