Device design for subthreshold slope and threshold voltage control in sub-100 nm fully-depleted SOI MOSFETs

Abstract

Device design issues regarding threshold voltage (V/sub th/) control, short channel effects (SCE) and subthreshold slope are quantitatively studied for fully-depleted (FD) SOI MOSFETs under the sub-100 nm regime. As for the Vth adjustment method, the combination of back gate bias (V/sub g2/) and gate work function (/spl Phi//sub m/) control is found to provide superior SCE, V/sub th/ fluctuation due to SOI thickness variation and current drive. As for the subthreshold slope (SS), on the other hand, the optimization of thickness and permittivity of buried oxides is a key issue. It is found that, when the gate length is less than 100 nm, SS has a minimum value at buried oxide thickness of around 40 nm, irrespective of SOI thickness. It is also shown that the reduction in the permittivity of buried oxides improves SS.