IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2003 · 150 citations · 13 references
EngineeringComputer EngineeringElectrical EngineeringHearing AidsLow-power DesignMicroelectronicsCmos Circuit DesignDigital Signal ProcessingDynamic Power ReductionHearing Aid Signal ProcessingLow-power Digital Circuit DesignSubthreshold Circuit DesignCmos Logic CircuitsCmos Logic DesignLow-power Cmos DesignPower-delay ProductStable Operation At Low PowerSubthreshold Cmos DesignSubthreshold OperationUltra-low-power Cmos
We present an ultra-low-power, delayed least mean square (DLMS) adaptive filter operating in the subthreshold region for hearing aid applications. Subthreshold operation was accomplished by using a parallel architecture with pseudo nMOS logic style. The parallel architecture enabled us to operate the system at a lower clock rate and reduced supply voltage while maintaining the same throughput. Pseudo nMOS logic operating in the subthreshold region (subpseudo nMOS) provided better power-delay product than subthreshold CMOS (sub-CMOS) logic. Simulation results show that the DLMS adaptive filter can operate at 22 kHz using a 400-mV supply voltage to achieve 91% improvement in power compared to a nonparallel, CMOS implementation. To validate the robust operation of subthreshold logics, a 0.35 /spl mu/m, 23.1 kHz, 21.4 nW, 8/spl times/8 carry save array multiplier test chip was fabricated where an adaptive body biasing scheme is used for compensating process, supply and temperature variations. The test chip showed stable operation at a supply voltage of 0.30 V, which is even lower than the threshold voltages of the pMOS (0.82 V) and nMOS (0.67 V) transistors.
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Steven C. Rogers · Control Engineering Practice · 1996 · 9.3K citations
Ultra-low power digital subthreshold logic circuits
H. Soeleman, Kaushik Roy · 1999 · 188 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +16