Characterization and suppression of drain coupling in submicrometer EPROM cells

Abstract

The EPROM transistor suffers from a capacitive-coupling-based short-channel effect called drain turn-on or V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dto</inf> that limits the maximum drain voltage. Several measurement techniques are demonstrated to characterize the V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dto</inf> effect. An analytical model is applied to the problem to estimate the effects of process variations to suppress the phenomenon. The effect of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dto</inf> on scaling is discussed, and circuit and device design techiques to reduce or eliminate this problem are discussed.