A 20-ns 128-kbit*4 high speed DRAM with 330-Mbit/s data rate

Abstract

The authors describe a high-speed DRAM (HSDRAM), designed primarily for high performance, while retaining the density advantage of the one-transistor DRAM cell. The 128-kb*4, 78-mm/sup 2/ chip shows a random access time of 20 ns and a column access time of 7.5 ns, measured at 5.0 V, 25 degrees C, and 50-pF load. A 256-b*4 high-speed page mode is provided which has 12-ns cycle into 60 pF, resulting in a data rate of 330 Mb/s. Additional measurements on HSDRAM further demonstrate that DRAM operation in a high-speed regime is not precluded by noise, power, wiring delay, and soft error rate. The device is implemented in a 1.0 mu m n-well CMOS process.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>