IEEE Journal of Solid-State Circuits · 1992 · 23 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignDigital Integrated CircuitsI/o ArchitectureIntegrated Circuit DesignMixed-signal Integrated Circuit DesignMixed-signal IntegrationCmos Analog Circuit DesignCmos Analog Integrated CircuitsHigh-speed Circuit DesignHigh-speed Cmos DesignHigh-speed I/o Circuit DesignI/o Buffer DesignImpedance Matching NetworksImpedance Matching Techniques
Very high-speed off-chip data rates have been difficult to achieve in CMOS technologies. An all-CMOS set of I/O buffer circuits, which use current-mode and impedance matching techniques, capable of transmitting off-chip at 1-Gb/s data rates is described. The circuits are also compatible with voltage-mode signal levels for ECL input and MOS output circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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A CMOS to 100 K ECL interface circuit
Martin Nors Pedersen, Peter Metz · 2003 · 23 citations