High-speed CMOS I/O buffer circuits

Abstract

Very high-speed off-chip data rates have been difficult to achieve in CMOS technologies. An all-CMOS set of I/O buffer circuits, which use current-mode and impedance matching techniques, capable of transmitting off-chip at 1-Gb/s data rates is described. The circuits are also compatible with voltage-mode signal levels for ECL input and MOS output circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>