A high performance BiCMOS technology using 0.25 mu m CMOS and double poly 47 GHz bipolar

Abstract

In this technology, first the CMOS is defined and a major part of the heat cycle is carried out. Then, the bipolar is fabricated by the rest of the CMOS. Patterned subcollector definition and epitaxial silicon growth are followed by the deep and shallow trench isolation processes. Next are the npn collector reach-through and anneal, CMOS well and threshold implants, gate oxidation and poly deposition. CMOS gate definition, reoxidation, and nMOS n/sup +/ implant. Electron-beam lithography is used to pattern the gate level in order to achieve a minimum gate poly width of 0.3 mu m. Next, the CMOS region is protected, while fabricating the bipolar. The annealing cycles for base and emitter during the process are compatible with the CMOS requirements. The minimum final emitter size is 0.5 mu m. CMOS ring oscillators with 50-ps delay per stage at 2.5-V supply, ECL ring oscillator delays of 48 ps at 1.2 mA, and fast loaded BiNMOS gate delays have been achieved.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>