2002 · 139 citations · 12 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureMicroelectronicsSemiconductor DevicesCmos Circuit DesignCombinational Logic DescriptionDevice ModelingDevice SimulationMixed-signal ModelingTiming ModelingCmos Digital Circuit DesignCombinational Logic DesignHeavy Ion RadiationHeavy-ion ScatteringLatch DesignMemory Circuit DesignSingle Event EffectsSingle Event Upset Modeling
The question to what extent particle induced transients in combinational parts of a circuit propagate into memory elements is addressed in this paper An experimental method is presented in which the proportion of bit flips originating from heavy-ion hits in combinational logic is determined. It is proposed that a voltage pulse may only propagate through a limited number of transistor stages and still be latched. The proportion of all transients in combinational logic that were latched into registers was experimentally, estimated to be between 0.7/spl middot/10/sup -3/ and 2/spl middot/10/sup -3/ for a custom designed CMOS circuit. Very few multiple bit flips were observed during the experiments which indicates that the single bit flip model used in many high-level simulations is reasonable accurate.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Using heavy-ion radiation to validate fault-handling mechanisms
Johan Karlsson, Peter Lidén, Peter Dahlgren et al. · IEEE Micro · 1994 · 177 citations
A logic-level model for α-particle hits in CMOS circuits
J.H. Patel · 2002 · 103 citations
Engineering, Computer Engineering, Electrical Engineering +17
A fast and accurate gate-level transient fault simulation environment
E.M. Rudnick, G.S. Choi, J.H. Patel et al. · 2002 · 46 citations
Engineering, Computer Engineering, Electrical Engineering +13