Ultra-low standby power (U-LSTP) 65-nm node CMOS technology utilizing HfSiON dielectric and body-biasing scheme

Abstract

This paper reports 65-nm node ultra-low standby power CMOS technology for mobile applications, utilizing the combination of HfSiON FET and back-biasing scheme for the first time. With well-optimized channel, offset-spacer and halo conditions, physical gate length is successfully scaled down to 55 nm with excellent V/sub th/ roll-off and small DIBL, for both surface channel nFET and buried channel pFET. The record I/sub on//I/sub off/ ratio, the drive current of 510/220 /spl mu/A//spl mu/m with off-state leakage of 20/20 pA//spl mu/m, are obtained. We have also demonstrated body-biasing scheme feasibility for further subthreshold leakage (I/sub subth/) reduction. By exploiting Fermi-level-pinning effect, we have reduced the channel doping concentration and suppressed gate induced drain leakage (I/sub GIDL/) even under reverse body-biasing condition. Total standby leakage (I/sub subth/+I/sub GIDL/+I/sub g/) are reduced to 1.4/0.32 pA//spl mu/m at V/sub dd/= 0.8 V and Vb= /spl plusmn/1 V, which is the smallest value ever reported for 65nm-node LSTP.