The comparative analysis of the efficiency of regular and pseudo-optimal topologies of networks-on-chip based on Netmaker

Abstract

The different approaches to the optimization of network communication subsystem on a chip are considered. The regular and pseudo-optimal topologies with 9 nodes, using System Verilog library Netmaker are modeled. It is shown, that the pseudo-optimal topologies are highly efficient for the cases of network design with the number of nodes and connecting lines not achieved, when using typical regular topologies.