Bump-less interconnect for next generation system packaging

Abstract

A concept of bump-less interconnect for the next generation system packaging was proposed previously. Here the bump-less interconnect is defined as an interconnect of a size below 10 /spl mu/m pitch between chip and substrate, or between chip and chip. Such ultra-fine pitch interconnection will be necessary to realize high speed systems such as chip on chip or 3-D configuration for highly integrated multi-chip system in packaging. Two requirements are considered: Firstly, a transmission structure called stacked-pair line will be adopted in the bus-line in boards, and secondly, the surface activated bonding, SAB, is used to enable such ultra-high dense interconnection. A model, which is called IMSI-model 2000, is presented as an example of high speed CPU-memory.