50 nm SOI CMOS transistors with ultra shallow junction using laser annealing and pre-amorphization implantation

Abstract

CMOS transistors with 50 nm physical gate length are fabricated by laser annealing (LA) combined with pre-amorphization implantation (PAI) on an SOI substrate. Very low energy laser annealing is made possible by the SOI substrate, resulting in a large process window margin without undesirable parasitic phenomena. The transistors fabricated by the proposed method show higher drive current and better short channel effects than conventionally rapid thermal annealed (RTA) devices.