Modelling and optimization of low pass continuous-time sigma delta modulators for clock jitter noise reduction

Abstract

This work presents a system level model of the clock jitter influence in certain types of continuous time sigma delta modulators. The model helps the design of such modulators by speeding up the simulations, predicting analytically the SNR degradation and providing a practical way to minimize the jitter sensitivity of the modulator. Simulations and theoretical developments are contrasted with measurements in a real chip.