Susana Patón - Concepedia

Author

Susana Patón

Universidad Carlos III de Madrid ORCID

Also Known As

Patón, Susana, S. Paton, S. Patón, Susan Paton, Susana Paton, Susana Patón

Publications

564

Citations

H-Index

Concepts

All Affiliations

Universidad Carlos III de Madrid Infineon Technologies (Austria)Universidad Politécnica de Madrid

About

Susana Patón is an author at Universidad Carlos III de Madrid specializing in computer engineering, engineering, and signal processing.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	7	7	223
2	Computer Engineering	7	7	371
3	Biomedical Engineering	1	1	15
4	Electrical Engineering	1	1	23
5	Antenna	1	1	23

Susana Patón

Publications

465

Citations

H-Index

Page 1

	Year	Citations
A 70-mW 300-MHz CMOS continuous-time /spl Sigma//spl Delta/ ADC with 15-MHz bandwidth and 11 bits of resolution Susana Patón, A. Di Giandomenico, Luis Hernández, IEEE Journal of Solid-State Circuits Active BlocksData ConverterMixed-signal Integrated CircuitAnalog DesignComputer Engineering	2004	165
Modelling and optimization of low pass continuous-time sigma delta modulators for clock jitter noise reduction Luis Hernández, Andreas Wiesbauer, Susana Patón, EngineeringClock Jitter InfluenceClock RecoveryData ConverterSystem Level Model	2004	66
VCO-based sigma delta modulator with PWM precoding Luis Hernández, Susana Patón, Enrique Prefasi Electronics Letters EngineeringData ConverterMixed-signal Integrated CircuitVco LinearityAnalog Design	2011	37
A 0.1 mm$^{2}$, Wide Bandwidth Continuous-Time $\Sigma\Delta$ ADC Based on a Time Encoding Quantizer in 0.13 $\mu$m CMOS Enrique Prefasi, Luis Hernández, Susana Patón, IEEE Journal of Solid-State Circuits Innovative Sigma-deltaEngineeringAnalog-to-digital ConverterThird Order ModulatorData Converter	2009	36
A 7 mW 20 MHz BW Time-Encoding Oversampling Converter Implemented in a 0.08 mm$^{2}$ 65 nm CMOS Circuit Enrique Prefasi, Susana Patón, Luis Hernández IEEE Journal of Solid-State Circuits Mw 20EngineeringAnalog-to-digital ConverterClock RecoveryData Converter	2011	24
A superregenerative receiver for phase and frequency modulated carriers Luis Hernández, Susana Patón Oscillator Pole LocationsElectrical EngineeringEngineeringSuperregenerative ReceiverOscillators	2003	23
A 1.2-MHz 10-bit Continuous-Time Sigma–Delta ADC Using a Time Encoding Quantizer Luis Hernández, Enrique Prefasi, Ernesto Pun, IEEE Transactions on Circuits & Systems II Express Briefs EngineeringMultibit QuantizerData ConverterClock RecoveryAnalog Design	2009	22
A 15 MHz bandwidth sigma-delta ADC with 11 bits of resolution in 0.13μm CMOS A. Di Giandomenico, Susana Patón, Andreas Wiesbauer, Active BlocksData ConverterMixed-signal Integrated CircuitAnalog DesignComputer Engineering	2004	21
Self-Adjustable Galvanic Skin Response Sensor for Physiological Monitoring José Miranda, Alba Páez-Montoro, C. López-Ongil, IEEE Sensors Journal Wearable SystemMedical MonitoringEngineeringWearable TechnologyWearable Sensors	2023	15
A 2-2 Discrete Time Cascaded &#x003A3;&#x00394; Modulator With NTF Zero Using Interstage Feedback Manuel Sánchez‐Renedo, Susana Patón, Luis Hernández Data ConverterMixed-signal Integrated CircuitAnalog DesignNoiseDigital Filter	2006	14

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