Optimized 60-V Lateral Dmos Devices for Vlsi Power Applications

Abstract

High-performance, 60-V, Lateral DMOS (LDMOS) devices have been studied for VLSI intelligent power applications, where, along with high analog and logic density, high-power density is also required. Through proper optimization with 2-D process and device simulations, a specific on-resistance of 1.24mΩ-cm^2 has been realized, using a minimum feature size of 1μm. This is the best reported performance level for an LDMOS device in this voltage range. The device uses a conventional structure which allows several isolated devices to be integrated on the same chip, permitting the fabrication of high-side, low-side, and H-bridge drivers for automotive and electronic data processing applications.