A scalable SCR compact model for ESD circuit simulation

Abstract

A scalable, compact model for SCR-based ESD-protection devices, which can simulate transient voltage overshoots observed on the timescale of charged device model (CDM) events, is presented. This model captures the effect that layout spacings have on SCR characteristics such as holding voltage and trigger current. Bias and time dependencies of SCR on-resistance are captured with a resistance model that accounts for self-heating and velocity saturation.