Design of low-voltage CMOS pipelined ADCs using 1 pico-Joule of energy per conversion

Abstract

This paper presents an optimization methodology based on genetic algorithms for designing low-voltage low-power pipelined ADCs. It is demonstrated that multi-bit rather than minimum resolution-per-stage architectures are better suited for low-voltage operation and also that, either switched-opamp or clock-boosting techniques can produce equivalent realizations in terms of power efficiency. By carefully tailoring the pipelined architecture with the proposed optimization approach it is clearly demonstrated by means of a 1.5V, 10b, 40 MS/s pipeline ADC design example that reducing the supply voltage does not necessarily increase the used energy per conversion.