A 14-bit 10-MHz calibration-free CMOS pipelined A/D converter

Abstract

A 14-bit 10-MHz sampling analog-to-digital converter has been realized without calibration in a double-poly 0.8 /spl mu/m CMOS process. The ADC utilizes a 4-stage pipelined architecture with a wide-band sample-and-hold amplifier and achieves the highest resolution reported to date at 10 MHz. The chip occupies a die area of 19 mm/sup 2/, uses a single 5 V supply voltage, and dissipates only 210 mW. Measured DNL and INL are /spl plusmn/0.7 LSB and /spl plusmn/2.5 LSB, respectively. The SNR and THD for a 1 MHz input signal are 81 dB and -87 dB, respectively.