1985 · 12 citations · 0 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureMicroelectronicsSemiconductor DevicesCmos Circuit DesignDevice ScalingMemory DevicesMemory Subsystem DesignPhysical DesignCmos Fabrication ProcessesCmos ReliabilityDie ArchitectureMemory Array ArchitectureMemory Circuit Design
Application of a divided bitline matrix architecture, combined with a 1.2μ double metal CMOS process has resulted in the development of a 5V 1Mb DRAM with an array area to die ratio of 56.6%. Over 80% of the total die area is repairable using laser programmed redundant rows and columns.