Novel input ESD protection circuit with substrate-triggering technique in a 0.25-μm shallow-trench-isolation CMOS technology

Abstract

A substrate-triggering technique, to increase the ESD robustness and to reduce the trigger voltage of the ESD protection device, is proposed to improve the ESD protection efficiency of the input ESD protection circuit in deep-submicron CMOS technology. Through suitable substrate-triggering design on the device structure, this proposed input ESD protection circuit can successfully protect the thinner gate oxide (50 /spl Aring/) of the input stage in a 0.25 /spl mu/m CMOS technology and sustain an ESD level above 2000 V without extra process modification.